1. Field of the Invention
The present invention relates to an output circuit using a field effect transistor (FET), and more particularly, to a source-coupled FET logic type output circuit.
2. Description of the Related Art
A conventional source coupled FET logic (hereinafter called SCFL) type output circuit is shown in FIG. 1. In the same figure, one electrode of a level shift element LS1 is coupled to a high-voltage power source V.sub.DD, with another electrode connected to a one electrode of load element LD and the drain electrode an FET Q1, respectively. Further, the other electrode of the load element LD is coupled to the drain electrode of another FET Q2, and also to the gate electrode of second another FET Q3 of which drain electrode is connected to the high-voltage power source V.sub.DD. The FETs Q1 and Q2 have their gate electrodes applied as respective input terminals IN and IN, and their respective source electrodes connected together and also connected to a low-voltage power source V.sub.SS through a constant current power source CC1. The source electrode of the FET Q3 is connected to the power source V.sub.SS by a constant current source CC2. The source electrode of the FET Q3 is connected to the low-voltage power source V.sub.SS by a resistor R. The source electrode of the FET Q3 is used as an output terminal, and is connected to the low-voltage power source VSS by a capacitive load C.sub.L.
In the SCFL type output circuit arranged such as the above, the input terminals IN and IN commonly have a complementary signal applied thereto, wherein if the input terminals IN and IN are set to a low level and a high level, respectively, the FET Q1 is turned off and the FET Q2 is turned on. The potential difference V.sub.GS between the gate and source electrodes of the FET Q3 therefore decreases, whereby the FET Q3 subsequently is turned off. This results in that the charge thus far stayed in the capacitive load C.sub.L is discharged via the resistor R, and thereby the output terminal OUT becomes to be of a low level.
Now, applying the SCFL type output circuit such configured as the above for a high-speed integrated circuit is preceded by a prerequisite that charging and discharging the capacitive C.sub.L must be implemented quickly. However, generally, the capacitive C.sub.L is greatly large as compared with the gate capacity of each FET incorporated in the SCFL type output circuit. This signifies that much time is required to discharge the capacitive load C.sub.L. Therefore, to meet the above-capacitive remarked prerequisite, it is needed to lessen the time of discharging by decreasing the resistance of the resistor R. But the past attempts thus far undertaken to reduce the resistance of resistor R came across a a problem that the power consumption went up in response to the flow of an unnecessarily large current for charging the capacitive load C.sub.L.